ics93718 idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ddr and sdram buffer datasheet description output features ddr & sdram fanout buffer, for via pro 266, kt266 and p4x266 ddr chipsets ? low skew, fanout buffer 1 to 12 differential clock distribution i 2 c for functional and output control feedback pin for input to output synchronization supports up to 4 ddr dimms or 3 sdram dimms + 2 ddr dimms frequency supports up to 200mhz (ddr400) supports power down mode for power mananagement cmos level control signal input key specifications output - output skew: <100ps output rise and fall time for ddr outputs: 500ps - 700ps duty cycle: 47% - 53% 48-pin ssop package available in rohs compliant packaging pin configuration funtional block diagram 48-pin ssop fb_out vdd3.3_2.5 gnd ddrt0_sdram0 ddrc0_sdram1 ddrt1_sdram2 ddrc1_sdram3 vdd3.3_2.5 gnd ddrt2_sdram4 ddrc2_sdram5 vdd3.3_2.5 buf_in gnd ddrt3_sdram6 ddrc3_sdram7 vdd3.3_2.5 gnd ddrt4_sdram8 ddrc4_sdram9 ddrt5_sdram10 ddrc5_sdram11 vdd3.3_2.5 sdata sel_ddr* vdd2.5 gnd ddrt11 ddrc11 ddrt10 ddrc10 vdd2.5 gnd ddrt9 ddrc9 vdd2.5 pd#* gnd ddrt8 ddrc8 vdd2.5 gnd ddrt7 ddrc7 ddrt6 ddrc6 gnd sclk ics93718 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 *internal pull-up resistor of 120k to vdd sclk s data sel_ddr* pd# buf_in control logic fb_out ddrt0_sdram0 ddrt1_sdram2 ddrt2_sdram4 ddrt3_sdram6 ddrt4_sdram8 ddrt5_sdram10 ddrt(11:6) ddrc0_sdram1 ddrc1_sdram3 ddrc2_sdram5 ddrc3_sdram7 ddrc4_sdram9 ddrc5_sdram11 ddrc (11:6) funtionality table e d o m8 4 n i p d d v 5 . 2 _ 3 . 3 n i p , 5 1 , 1 1 , 0 1 , 7 , 6 , 5 , 4 2 2 , 1 2 , 0 2 , 9 1 , 6 1 r d d e d o m 1 = r d d _ l e sv 5 . 2 e b l l i w s t u p t u o e s e h t s t u p t u o r d d d s / r d d e d o m 0 = r d d _ l e sv 3 . 3 e b l l i w s t u p t u o e s e h t m a r d s d r a d n a t s s t u p t u o
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer pin description r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1t u o _ b ft u ok c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f , 3 2 , 7 1 , 2 1 , 8 , 25 . 2 _ 3 . 3 d d vr w p s n i p o t y l p p u s e g a t l o v v 3 . 3 r o v 5 . 2 2 2 , 1 2 , 0 2 , 9 1 , 6 1 , 5 1 , 1 1 , 0 1 , 7 , 6 , 5 , 4 , 6 2 , 8 1 , 4 1 , 9 , 3 6 4 , 0 4 , 5 3 , 1 3 d n gr w pd n u o r g , 9 3 , 3 4 , 5 4 , 8 2 , 0 3 , 4 3 t r d d) 6 : 1 1 (t u o. s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " , 8 3 , 2 4 , 4 4 , 7 2 , 9 2 , 3 3 ) 6 : 1 1 ( c r d dt u o. s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c " 4 , 6 , 0 1 , 5 1 , 9 1 , 1 2 ) 0 : 5 ( t r d d ) 0 , 2 , 4 , 6 , 8 , 0 1 ( m a r d s t u o m a r d s v 3 . 3 r o , s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " t u p n i r d d _ l e s n o g n i d n e p e d s t u p t u o k c o l c 5 , 7 , 1 1 , 6 1 , 0 2 , 2 2 ) 0 : 5 ( c r d d , 3 , 5 , 7 , 9 , 1 1 ( m a r d s ) , 1 t u o s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r o t n e m e l p m o c "v 3 . 3 r o , t u p n i r d d _ l e s n o g n i d n e p e d s t u p t u o k c o l c m a r d s 3 1n i _ f u bn it u p n i r e f f u b d e d n e e l g n i s 4 2a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 5 2k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 7 4 , 1 4 , 7 3 , 2 35 . 2 d d vr w py l p p u s e g a t l o v v 5 . 2 6 3# d pn i e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i e c i v e d r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h t . d e l b a s i d . s m 3 n a h t 8 4r d d _ l e sn i e d o m d s / r d d r o e d o m r d d r o f t u p n i t c e l e s e d o m r d d = 1 e d o m d s / r d d = 0
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. controller (host) ics (slave/receiver) start bit address d4 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 7 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d5 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 7 stop bit how to read: general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 6 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d5 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 7 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes:
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer byte 6: output control (1= enable, 0 = disable) byte 7: output control (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b8 41 ) y l n o k c a b d a e r ( r d d _ l e s 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b4 4 , 5 41 1 1 c r d d , 1 1 t r d d 2 t i b2 4 , 3 41 0 1 c r d d , 0 1 t r d d 1 t i b8 3 , 9 31 9 c r d d , 9 t r d d 0 t i b3 3 , 4 31 8 c r d d , 8 t r d d t i b# n i pd w pn o i t p i r c s e d 7 t i b9 2 , 0 31 7 c r d d , 7 t r d d 6 t i b7 2 , 8 21 6 c r d d , 6 t r d d 5 t i b2 2 , 1 21 0 1 m a r d s , 5 t r d d 1 1 m a r d s _ 5 c r d d 4 t i b0 2 , 9 11 8 m a r d s _ 4 t r d d 9 m a r d s _ 4 c r d d 3 t i b6 1 , 5 11 6 m a r d s _ 3 t r d d 7 m a r d s _ 3 c r d d 2 t i b1 1 , 0 11 4 m a r d s _ 2 t r d d 5 m a r d s _ 2 c r d d 1 t i b7 , 61 2 m a r d s _ 1 t r d d 3 m a r d s _ 1 c r d d 0 t i b5 , 41 1 m a r d s _ 0 t r d d 0 m a r d s _ 0 c r d d
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer absolute max electrical characteristics - input/supply/common output parameters recommended operating condition supply voltage (vdd & vdd2.5) -0.5v to 3.6v logic inputs gnd ?0.5 v to v dd +0.5 v ambient operating temperature 0c to +85c case temperature 115c storage temperature ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. sel_ddr = 0 sdram outputs v dd = 3.3v, t a = 0 - 85c; (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 110a input low current i il v i = v dd or gnd -100 -20 a i dd3.3_2.5 c l = 0pf, 133mhz 200 250 ma i dd2. 5 c l = 0pf, 133mhz 100 200 ma i ddpd c l = 0pf, all frequencies 310ma output high current i oh v dd = 3.3v , v out = 1v -74 -18 ma output low current i ol v dd = 3.3v , v ou t = 1.2v 26 42 ma v dd = 3.3v, v oh = -12ma v dd = 3.3v i oh = 12ma input capacitance 1 c in v i = gnd or v dd 2pf 1 guaranteed by design, not 100% tested in production. operating supply current high-level output voltage v oh 2v low-level output voltage v ol 0.4 0.35 2.95 sel_ddr=0 sdram outputs v dd =3.3v , t a = 0 - 85c; (unless otherwise stated) parameter symbol conditions min typ max units v dd3.3_2.5 3.0 3.3 3.6 v dd2. 5 2.3 2.5 2.7 input high voltage v ih sel_ddr, pd# input 2.0 v input low voltage v il sel_ddr, pd# input 0.8 v input voltage level v in v dd v 1 guaranteed by design, not 100% tested in production. v power supply voltage
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer sel_ddr = 1 ddr/ddr_sdram outputs v dd =2.5, t a = 0 - 85c; (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v d d or gnd 110a input low current i il v i = v d d or gnd -100 -25 a i dd2. 5 c l = 0pf, 133mhz 76 200 ma i ddpd c l = 0pf, all 310ma output high current i oh v d d = 2.5v , v out = 1v -74.5 -18 ma output low current i ol v dd = 2.5v , v out = 26 42.5 ma v d d = 2.5v, v oh = -12ma v d d = 2.5v i oh = 12ma output differential-pair crossing volta g e v oc (v dd/ 2) ?0.1 1.25 (v dd/ 2) +0.1 v input capacitance 1 c in v i = gnd or v dd 2pf 1 guaranteed by design, not 100% tested in production. v low-level output voltage v ol 0.46 2.3 0.35 operating supply current high-level output voltage v oh 1.7 sel_ddr=1 ddr/ddr_sdram outputs = 2.5v , t a = 0 - 85c (unless otherwise stated) parameter symbol conditions min typ max units v dd3.3_2.5 2.3 2.5 2.7 v dd2. 5 2.3 2.5 2.7 input high voltage v ih sel_ddr, pd# input 2.0 v input low voltage v il sel_ddr, pd# input 0.8 v input voltage level v in v dd v 1 guaranteed by design, not 100% tested in production. v power supply voltage electrical characteristics - input/supply/common output parameters recommended operating condition
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer ddr_mode (sel_ddr = 1), vdd = 2.55% parameter symbol condition min typ max units operating frequency 66 133 200 mhz input clock duty cycle d tin 40 50 60 % output to output skew t skew output crossover skew ddr[0:11] 80 100 ps 66mhz to 100mhz, w/loads 48 49 52 % 101mhz to 167mhz, w/loads 47 50 53 % rise time, fall time (ddr outputs) trd, tfd measured between 20% and 80% output, w/loads 500 600 700 ps duty cycle d c 2 switching characteristics sd_mode (sel_ddr = 0), vdd = 3.35% parameter symbol condition min typ max units operating frequency 66 133 200 mhz input clock duty cycle d tin 40 50 60 % output to output skew t skew v t = 1.50v 150 ps duty cycle d c 2 66mhz to 200mhz 54 % rise time, fall time (sdram outputs) trs, tfs v ol = 0.4v, v oh = 2.4v, w/loads 0.5 1.5 1.7 ns sdram buffer lh prop. delay 1 t plh input edge greater than 1v/ns 2 2.5 ns sdram bufer hl prop. delay 1 t phl input edge greater than 1v/ns 1.9 2.5 ns notes: 1. refers to transition on non-inverting output. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t2/t1, were the cycle (t1) decreases as the frequency goes up. switching characteristics
idt tm /ics tm ddr and sdram buffer ics93718 rev e 02/11/07 ics93718 ddr and sdram buffer ordering information ics93718 y flft designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f lf - t 300 mil ssop index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 variations min max min max 48 15.75 16.00 .620 .630 10-0034 reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions
ics93718 ddr and sdram buffer innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm
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